The present invention relates to a process for the positioning of an interconnection line on an electrical contact hole of an integrated circuit. This positioning process is more particularly usable in the production of MOS (metal-oxide-semiconductor) integrated circuits.
FIG. 1 is a sectional view illustrating the prior art procedure for positioning an interconnection line on an electrical contact hole of an integrated circuit. The integrated circuit 2 comprises a doped semiconducting, active zone 4, corresponding for example to the source or drain of a MOS transistor, which is to be electrically connected to another, not shown, active zone of the integrated circuit. This active zone 4 is covered by an oxide layer 6, in which is formed the electrical contact hole 8 of said active zone 4, by cutting the oxide layer by chemical etching through a suitable mask disposed on the layer. The interconnection of the active zone 4 and the other active zone of the integrated circuit is brought about by covering the complete integrated circuit with a conducting layer 10, then chemically etching the latter through an appropriate mask disposed on the conducting layer.
To prevent etching of the material (silicon) of the active zone 4 of integrated circuit 2 during the etching of the interconnection line in conducting layer 10, it is necessary for the latter to cover not only the electrical contact hole 8, but also a good part of the oxide layer 6, located on either side of said hole. Unfortunately, the fact that conductive layer 10 overlaps the contact hole 8, limits the integration density of this integrated circuit.